The subject matter disclosed herein relates to integrated circuits. More particularly, the subject matter relates to integrated circuit structures, e.g., bi-polar junction complimentary metal-on-oxide semiconductor (BiCMOS) structures.
As devices relying upon integrated circuits (ICs) have increased in complexity and functionality, those devices have required ever more dynamic ICs to meet the demands of those device users. For example, in BiCMOS IC structures, p-type; n-type; p-type (PNP) transistor regions are generally slower (for switching) than NPN transistor regions. However, a vertical PNP transistor region can exhibit relatively high switching speeds when the n-type region is thinned, allowing for faster transmission between p-type regions. The vertical PNP transistor built according to conventional approaches, however, requires several different mask steps (and distinct masks) in order to form, and can result in a large collector-base (CB) junction, which contributes to parasitic losses. These parasitic loses can negatively effect the performance of the BiCMOS having the PNP transistor region.